1. Field of the Invention
The present invention relates to high-voltage gate drivers and, more particularly, to a high-voltage gate driver that drives Group III-N high electron mobility transistors.
2. Description of the Related Art
The LM5100A/LM5101A is a high-voltage gate driver manufactured by National Semiconductor Corporation of Santa Clara, Calif. that, along with a boot strap capacitor, independently drives both the high side and the low side n-channel MOSFETs in a synchronous buck converter or a half-bridge configuration.
FIG. 1 shows a schematic diagram that illustrates an example of a conventional step down circuit 100. As shown in FIG. 1, step down circuit 100 includes a gate driver 110 that has a lower driver circuit 112, an upper driver circuit 114, and a diode D1 that connects lower driver circuit 112 to upper driver circuit 114. Gate driver 110 can be implemented with, for example, a LM5100A/LM5101A gate driver.
As further shown in FIG. 1, lower driver circuit 112 includes a comparator 120 that is connected to a low input LI to receive a low input signal, and a driver 122 that receives the output from comparator 120. Driver 122, which is conventionally implemented, includes a drive circuit 124 and an output inverter 126 that is connected to drive circuit 124. Output inverter 126, in turn, includes a PMOS transistor P1 and a NMOS transistor N1.
PMOS transistor P1 has a source connected to an upper rail UR1, a drain connected to a low signal output LO, and a gate connected to the output of drive circuit 124. NMOS transistor N1 has a source connected to a lower rail LR1, a drain connected to the low signal output LO, and a gate connected to the output of drive circuit 124. Upper rail UR1 is connected to a power supply input VDDI to receive a power supply voltage VDD, while lower rail LR1 is connected to a ground input VSSI to receive ground.
Upper driver circuit 114 includes a comparator 130 that is connected to a high input HI to receive a high input signal, a level shifter 132 that receives the output from comparator 130, and a driver 134 that receives the output from level shifter 132. Driver 134, which is conventionally implemented, includes a drive circuit 136 and an output inverter 138 that is connected to drive circuit 136. Output inverter 138, in turn, includes a PMOS transistor P2 and a NMOS transistor N2.
PMOS transistor P2 has a source connected to an upper rail UR2, a drain connected to a high signal output HO, and a gate connected to the output of drive circuit 136. NMOS transistor N2 has a source connected to a lower rail LR2, a drain connected to the high signal output HO, and a gate connected to the output of drive circuit 136. Upper rail UR2 has an external connection HB, while lower rail LR2 has an external connection HS. In addition, diode D1 has an anode connected to the upper rail UR1 and a cathode connected to the upper rail UR2.
As additionally shown in FIG. 1, step down circuit 100 includes a power supply smoothing capacitor C1 that is connected to the power supply input VDDI and the ground input VSSI, and a boot strap capacitor C2 that is connected to the external connection HB (and thereby upper rail UR2) and the external connection HS (and thereby lower rail LR2).
Further, step down circuit 100 includes a synchronous buck converter 140 that is connected to gate driver 110. Buck converter 140 includes a lower NMOS transistor Q1 and an upper NMOS transistor Q2. Lower NMOS transistor Q1 has a source connected to ground, a drain connected to the external connection HS (and thereby lower rail LR2), and a gate connected to the low signal output LO.
Upper NMOS transistor Q2 has a drain connected to a power supply voltage VCC, a source connected to the external connection HS (and thereby lower rail LR2), and a gate connected to the high signal output HO. Power supply voltage VCC can be substantially larger than power supply voltage VDD, e.g., 100V versus 5V.
In addition, buck converter 140 also includes an inductor L, a buck capacitor C3, and a load 142. Inductor L has a first end that is connected to the external connection HS (and thereby lower rail LR2), while buck capacitor C3 and load 142 are both connected between a second end of inductor L and ground.
In operation, when the low input signal received by low input LI is a logic high and the high input signal received by high input HI is a logic low, drive circuit 124 outputs a logic low and drive circuit 136 outputs a logic high. The output from drive circuit 124 turns on PMOS transistor P1 and turns off NMOS transistor N1 of output inverter 126, while the output from drive circuit 136 turns on NMOS transistor N2 and turns off PMOS transistor P2 of output inverter 138.
When PMOS transistor P1 turns on, PMOS transistor P1 places the power supply voltage VDD on the gate of NMOS transistor Q1, which turns on transistor Q1. During initial start up, when NMOS transistor Q1 turns on, transistor Q1 places ground on the bottom plate of boot strap capacitor C2, which causes the top plate of boot strap capacitor C2 to charge up to the power supply voltage VDD less the voltage drop VD1 across diode D1, or VDD−VD1. When NMOS transistor N2 turns on, NMOS transistor N2 places ground on the gate of NMOS transistor Q2, which turns off transistor Q2.
When the signals input to gate driver 110 are to change states, the low input signal received by low input LI changes state to a logic low before the high input signal received by high input HI changes state to a logic high which, in turn, causes the output of driver 122 to change state before the output of driver 134 changes state. This is to insure that no shoot through current can flow through upper transistor Q2 and lower transistor Q1 to ground. (The timing of the low input signal and the high input signal are externally controlled.)
When the low input signal received by low input LI changes state to a logic low, the output of drive circuit 124 changes state and outputs a logic high. The logic high turns off PMOS transistor P1 and turns on NMOS transistor N1. When NMOS transistor N1 turns on, NMOS transistor N1 places ground on the gate of NMOS transistor Q1, which turns off NMOS transistor Q1.
When the high input signal received by high input HI next changes state to a logic high, the output of drive circuit 136 changes state and outputs a logic low. The logic low turns on PMOS transistor P2 and turns off NMOS transistor N1. When PMOS transistor P2 turns on, the voltage VDD−VD1 on the top plate of boot strap capacitor C2 charges up the gate of NMOS transistor Q2 to turn on transistor Q2.
Thus, when PMOS transistor P2 turns on, a finite or fixed amount of charge is taken from boot strap capacitor C2 to turn on transistor Q2. (Although the voltage on the top plate of boot strap capacitor C2 is slightly less than the voltage VDD−VD1 after turning on transistor Q2, the following discussion assumes that the voltage on the top plate of boot strap capacitor C2 continues to be equal to VDD−VD1 for simplicity.)
When NMOS transistor Q2 turns on, a current flows through NMOS transistor Q2 and inductor L to charge up buck capacitor C3 and provide current to load 142. In addition, the voltage on the source of NMOS transistor Q2 and the bottom plate of boot strap capacitor C2 rises to the power supply voltage VCC. The rising voltage on the bottom plate of boot strap capacitor C2 pushes up the voltage on the top plate of boot strap capacitor C2 to a voltage equal to VDD−VD1+VCC, which is also placed on the gate of transistor Q2.
However, since the voltage on the source of NMOS transistor Q2 is equal to the power supply voltage VCC, the gate-to-source voltage of NMOS transistor Q2 remains equal to VDD−VD1 ((VDD−VD1+VCC)−VCC). Thus, even though the voltage on the source of NMOS transistor Q2 can rise to value of, for example, 100V, the voltage has no effect on the operation of NMOS transistor Q2.
When the signals input to gate driver 110 are to change states again, the high input signal received by high input HI changes state to a logic low before the low input signal received by low input LI changes state to a logic high to prevent a shoot through current which, in turn, causes the output of driver 134 to change state before the output of driver 122 changes state.
When the high input signal received by high input HI changes state to a logic low, the output of drive circuit 136 changes state and outputs a logic high. The logic high turns on NMOS transistor N2 and turns off PMOS transistor P2. When NMOS transistor N2 turns on, the voltage on the gate of NMOS transistor Q2 falls, and turns off NMOS transistor Q2 when the voltage on the gate of transistor Q2 is less than a threshold voltage above the voltage on the source of NMOS transistor Q2.
Due to the energy stored in inductor L, inductor L continues to source current to buck capacitor C3 and load 142. To do this, inductor L pulls the voltage on the gate and source of NMOS transistor Q2, along with the voltage on the bottom plate of boot strap capacitor C2, down to a voltage of −VD2, where the voltage −VD2 is the voltage drop across the body diode of NMOS transistor Q1.
As the voltage on the bottom plate of boot strap capacitor C2 falls from the power supply voltage VCC to ground, the voltage on the top plate of boot strap capacitor C2 also falls from VDD−VD1+VCC to VDD−VD1. However, as the voltage on the bottom plate of boot strap capacitor C2 falls from ground to −VD2, the voltage across boot strap capacitor C2 is charged up by way of diode D1 to VDD−VD1+VD2.
When the low input signal received by low input LI next changes state to a logic high, the output of drive circuit 124 changes state and outputs a logic low. The logic low turns on PMOS transistor P1 and turns off NMOS transistor N1. When PMOS transistor P1 turns on, PMOS transistor P1 places the power supply voltage VDD on the gate of NMOS transistor Q1, which turns on transistor Q1. When NMOS transistor Q1 turns on, transistor Q1 closes a loop which lets a current flow from inductor L through load 142 and back through NMOS transistor Q1 to inductor L.
When the signals input to gate driver 110 next change states, the low input signal received by low input LI changes state to a logic low before the high input signal received by high input HI changes state to a logic high to prevent a shoot through current which, in turn, causes the output of driver 122 to change state before the output of driver 134 changes state.
When the low input signal received by low input LI changes state to a logic low, the output of drive circuit 124 changes state and outputs a logic high. The logic high turns off PMOS transistor P1 and turns on NMOS transistor N1. When NMOS transistor N1 turns on, NMOS transistor N1 places ground on the gate of NMOS transistor Q1, which turns off NMOS transistor Q1. At this time, the external connection HS (and thereby lower rail LR2) swings negative again and refreshes the charge across boot strap capacitor C2 to VDD−VD1+VD2.
When the high input signal received by high input HI next changes state to a logic high, the output of drive circuit 136 changes state and outputs a logic low. The logic low turns on PMOS transistor P2 and turns off NMOS transistor N2. When PMOS transistor P2 turns on, the charged up voltage VDD−VD1+VD2 on the top plate of boot strap capacitor C2 charges up the gate of NMOS transistor Q2 to turn on NMOS transistor Q2.
When NMOS transistor Q2 turns on, a current again flows through NMOS transistor Q2 and through inductor L to charge up buck capacitor C3 and provide current to load 142. In addition, the voltage on the source of NMOS transistor Q2 rises from the voltage −VD2 to the power supply voltage VCC.
Thus, when NMOS transistor Q2 is turned on, the gate-to-source voltage of NMOS transistor Q2 is equal to VDD−VD1+VD2. Since transistor Q1 is implemented as a MOS transistor, the voltage drop VD1 of diode D1 and the voltage drop VD2 of the body diode of transistor Q1 are approximately equal (e.g., 0.7V) and cancel each other out. As a result, the gate-to-source voltage of NMOS transistor Q2 is approximately equal to VDD−VD1+VD2, or VDD.
However, when transistors Q1 and Q2 are each implemented with a Group III-N high electron mobility transistor (HEMT), such as a GaN transistor, rather than MOS transistors, the voltage drop across transistor Q1 is much larger. For example, a GaN transistor has no body diode. As a result, when transistors Q1 and Q2 are both turned off, the voltage on the bottom plate of boot strap capacitor C2 is pulled down to approximately 2.5V before transistor Q1 turns on in reverse. Thus, substituting in exemplary numbers for the gate-to-source voltage of VDD−VD1+VD2 yields 5V−0.7V+2.5V or 6.8V, when transistor Q2 is implemented with a GaN transistor.
Although MOS transistors can withstand gate-to-source voltages of up to 20V, GaN transistors are damaged when the gate-to-source voltage exceeds approximately 6.0V. Over a period of time, this damage will result in the failure of the GaN transistors. As a result, GaN transistors can not be reliably substituted for NMOS transistors Q1 and Q2. Thus, there is a need for a circuit which can utilize a Group III-N HEMT in lieu of each of the NMOS transistors Q1 and Q2 without damaging the Group III-N HEMT utilized for transistor Q2.